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Design for Testability

DfT techniques add certain testability features to a microelectronic hardware product design.

Indeed, those features make it easier to develop and apply manufacturing tests for the designed hardware. Thus, test programs development and the application of manufacturing tests are simplified if appropriate DfT rules and suggestions are implemented.

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The purpose of manufacturing tests is to validate that the product hardware contains no defects. Indeed, defects may otherwise, adversely affect the product’s correct functioning. Tests are applied at several steps in the hardware manufacturing flow and, for certain product, may also be used for hardware maintenance in the customer’s environment.

Tests are generally driven by test programs that execute in Automatic Test Equipment (ATE) or, in the case of system maintenance, inside the assembled system itself. In addition to finding and indicating the presence of defects (i.e., the test fails), tests are able to indentify the nature of the encountered test fails. The diagnostic information can be used to locate the source of the failure. DfT plays an important role in  both the test program development and as an interface for test applicaton and diagnostics.

Design for Assembly

DfA techniques take in consideration the ease of assembly.

If a product contains fewer parts or if its features are easier to grasp, move, orient and insert; it will reduce assembly time thereby reduce assembly costs.

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Reducing the number of parts in an assembly generally reduces the total cost of parts in the assembly.

Indeed, when applying DfA techniques major cost benefits can occur on the overall project.

Design for Manufacturability

DfM techniques modify the design of integrated circuits (IC).

Thus, those modifications improve their production process, i.e.,  their functional yield, parametric yield, or their reliability.

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Traditionally, in the pre-nanometer aera, DfM consisted of a set of different methodologies trying to enforce some recommended design rules regarding the shapes and polygons of the physical layout of an IC. These DfM methodologies worked primarily at the full chip level. Additionally, worst-case simulations at different levels of abstraction were applied to minimize the impact of process variations on performance and other types of parametric yield loss. All these different types of worst-case simulations were essentially based on a set of worst-case SPICE device parameter files that were intended to represent the variability of transistor performance over the full range of variation in a fabrication process. Achieving high-yielding designs, VLSI technology has become an extremely challenging task due to the miniaturization as well as the complexity of leading-edge products.

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